Dialite

Temento

ON-CHIP INSTRUMENTATION, DEBUGGING AND VERIFICATION TOOL

DiaLite is an On-Chip instrumentation tool that sets a new way to monitor and debug complex designs for any type of FPGA. With DiaLite, you simply choose test IPs like triggers or logic analyzers that you seamlessly embed into your design. Once your usual flow is performed (Synthesis, Placing, Routing), you can run your design with its embedded instrumentation. DiaLite allows you to monitor your instruments, analyze logic signals and transactions, record logic events data and much more!

All Segments, From FPGA to SoC

There are 3 DiaLite Editions, each addressing specific needs and providing the specific debugging and verification tools you need :

  • DiaLite Leading Edge
  • DiaLite Power Edge
  • DiaLite Platform

They range from the basic logical instruments and waveform view to Assertion Checker, HDL Fault Finder and Code Viewer. All editions can be extended and complemented according to the verification level you expect and your device target, from small FPGA to SoC.

DiaLite Leading Edge

Designed to be independent from any FPGA or PLD target, DiaLite tool fits easily with any standard design flow that uses a HDL synthesis tool. During the Design Level of your hardware, the DiaLite Core library allows you to choose and insert the IP instruments you need to perform your debug process.

Dialite Leading Edge Flow At this Debug Level, you are now ready for the “Chip Debugging” step of the process. Your design runs jointly with your embedded instrumentation while DiaLite provides you with all the tools to Control and Display your IP cores.

You can now easily debug your design at speed, analyze logic signal levels and transactions, monitor busses and record logic events.

Debug cores are then automatically generated with the provided parameters and connected to the internal signals and busses.

These cores are inserted into Verilog or VHDL code. The design is then synthesized, placed and routed using the most current synthesis tools available on the market. The bitstreams are finally downloaded into the FPGA with a JTAG controller device.

Download DiaLite Leading Edge Brochure

DiaLite Power Edge

DiaLite™ Power Edge provides an unrivaled environment and collection of test IPs to verify and debug your FPGA based system designs:

Debug your Design Code On-Chip at Design Speed With a powerful and wide range of IPs, DiaLite™ increases the verification and debugging capabilities of your design or system environment based on FPGA or prototyping platform. IP cores can be combined and associated with multiple trigger conditions to build specific instrumentation and capture data in real-time. The easy connectivity and extended communication potential of a debugging strategy based on DiaLite™ will save you months of debugging efforts.

DialitePE_JointViews

A Technology that leads you directly to the Code Error

The HDL Fault Finder IP allows you to insert WatchPoints and BreakPoints into your HDL code and run concurrently with your signals instrumentation. The HDL Fault Finder provides an accurate monitoring and display of logic events occurring during your debugging session. By simply using a trigger on a signal having suspicious behavior and connecting this trigger as a hardware breakpoint to the HDL Fault Finder, you will be directly pointed to the last lines of code that were executed before the error occurred.

HDL Fault Finder details
Download a Dialite Power Edge Brochure

DiaLite Platform

DiaLite Platform Edition is the most complete and powerful tool available on the market to verify and debug your SoC or FPGA. The Platform Edition includes all features of the Power Edge Edition plus the Assertion Checker (AC) module. This IP allows designers to embed their system assertion conditions along with their system specifications before synthesis and then check them at speed.

Dialite Platform Flow

The Assertion Checker is built on the PSL and SVA standard, which makes all your format verification tests and system properties reusable.

Unlike conventional format verification, the “On-Chip Assertions” approach allows you to skip extensive processing run time and so cover possible behavior deviations at the system level.

DiaLite Platform Edition is thus well adapted to complex test scenarios involving race hazards and asynchrounous events.

While your design is running at full speed, the On-Chip Verification Process monitors and checks that your properties are not infringed.  The cover directive even gives you metrication for your verification process. 

Assertion Checker details
Download Dialite Platform Brochure