I this section You’ll find all detailed training material that will allow you to aquire all know how about the following topics: 1. GUI/Batch mode (Basics of operation in GUI and batch mode; scripter modes) 2. Design Entry (Using the HDL Editor) 3. Libraries (Creating, mapping, refreshing, encrypting simulation libraries) 4. HDL compilation (Compiling HDL files and EDIF netlist) 5. Simulation (Simulation initialization) 6. Debugging (HDL code tracing, simulation breakpoints, watch window, list viewer, waveform viewer, memory viewer, processes window, process stack window, advance dataflow viewer) 7. Code Coverage and Toggle Coverage (Getting code coverage and toggle coverage statistics for the design; merging coverage reports) 8. Design Profiler (Profiling the simulation time of the design) 9. PLI Applications (Compiling and running the PLI application) 10. Assertion Based Verification (Using OVA, PSL and SystemVerilog(assertion subset) languages) 11. SLP Simulation (Using accelerated simulation engine for Verilog designs) 12. Comparing Waveforms (How to compare ASDB and VCD waveform files) 13. SystemC Simulation (Native SystemC simulation)
