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2008-04-28
Aldec Joins Altera DO-254 Global Partner Network Providing In-Hardware Verification of Altera’s FPGA Devices
Aldec, Inc. today announced a comprehensive in-hardware verification solution that supports Altera Corporation (NASDAQ: ALTR) customers with DO-254 compliance projects. The global partnership combines Altera’s FPGA and HardCopy ASIC devices with Aldec’s DO-254 Compliance Tool Set (CTS), creating an in-hardware verification solution addressing Level A and Level B compliance requirements of the RTCA DO-254 specification.
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2008-03-04
Seminario Aldec “Innovative Design Methodologies for FPGA productivity”
EdaWay ed Aldec hanno il piacere di invitarLa al Seminario gratuito “Innovative Design Methodologies for FPGA productivity”, che si terrà il giorno 04 Marzo 2008 dalle ore 09.00 alle ore 17.00 presso l’Hotel Le Moran - Viale Europa, 90 - Cusago (MI).
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2008-02-26
Aldec Releases Riviera-PRO(TM) 2008.02 with VHDL 2007, SystemC 2.2 and SystemVerilog (DPI)
Aldec, Inc. announced today the release of Riviera-PRO 2008.02, a mixed language HDL simulator that now includes VHDL 2007, integrated SystemC 2.2 compiler and SystemVerilog DPI support.
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2007-09-26
EMPIRE XCcel 5.13
Now available the new EMPIRE XCCel release 5.13
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2007-05-25
EMPIRE XCcel 5.1
Empire XCcel™ 5.1- The ultimate EM simulation tool for microwave engineers
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2007-05-15
MicroStripes 7.51
MicroStripes 7.51 now available to download for existing customers.
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2007-02-28
MicroStripes 7.5
MicroStripes 7.5 now available to download for existing customers.
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2006-10-31
Released version XCcel
Empire XCcel™ - The ultimate EM simulation tool for microwave engineers
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2006-09-15
Empire XCcel
The new version of IMST full 3D EM Field simulator will be released soon
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2006-08-31
Aldec European Web Seminar Series
An Introduction to Assertions
Wednesday, September 6, 2006 at 4:00PM (France, Germany, Italy).
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2006-07-07
Synplicity Open IP Protection Flow in Riviera
ALDEC, Inc. in cooperation with Synplicity®, Inc., introduces a new methodology of handling IP protection in simulation and synthesis, compatible with the recently published Verilog standard IEEE Std 1364-2005 and forthcoming VHDL 2006 standard.
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2006-06-07
Synplicity Open IP Encryption Flow
An Open IP Encryption Flow Permits Industry-Wide Interoperability
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2006-01-04
SLP - System-Level Platform Simulation Technology
Aldec Delivers Next Generation of Simulation Technology
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