News da EDAWAY.COM http://www.edaway.com Mon, 12 May 2008 09:33:58 +0100 FeedCreator 1.7.2 http://www.edaway.com/news.php?action=details&id_news=22 nullRead More]]> info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=20 info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=21 Riviera-PRO offers mixed language verification support for VHDL, Verilog(R), SystemVerilog and SystemC for behavioral, structural and timing simulation of multi-million gate ASIC and FPGA designs. Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC, C/C++, Assertions and EDIF. Riviera-PRO works in command line mode for maximum speed or in state-of-the-art GUI for enhanced editing, tracing, and debugging capabilities, including code coverage and linting. Riviera-PRO is compatible with industry standards and interfaces with popular EDA products such as Synopsys(R) SmartModels(TM), LMTV(TM), Novas(TM), Denali(R), MATLAB(R), and Simulink(R). CLICK HERE to read the complete Press Release]]> info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=19 info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=18
Windows Vista Compatibility;
64 bit support for Windows XP and Vista;
Accelerated GUI for very complex structures;
Expert based automatic meshing;
Improved management of imported 3D data;
Speed improvement of open boundary conditions;
Further Kernel speed up (900 MCells / sec);
Lossy Meta Materials Support;

Further details at:

EMPIRE XCcel web site]]> info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=17 info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=15 http://www.flomerics.com/microstripes]]> info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=14 info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=13 The XCcel is now twice as fast with Kernel speeds processing up to 450 Mcells/sec, producing very accurate results. Wizards, Templates and its high speed processing makes Xccel the tool of choice for engineering professionals. XCcel features new modules such as Meta Materials, a powerful OPTIMIZER and parallel computing.
If reducing time-to-market, lowering costs and improving design are important to you, then you must consider the XCcel as an indispensable addition to your range of design tools.
This superb and powerful simulator is very much affordable and costs much less compared to other simulators in the market.
XCcel comes with full support provided by engineers at IMST experienced in the study of a wide range of microwave and radio frequency applications. ]]> info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=11
Agenda:

- Overview of OVL – Sources and Versions
- OVL Compilation and Management
- Using OVL with HDLs
- Important Global Defines (constants).
- OVL Checkers for Assertions and Functional Coverage

CLICK HERE to register for AVMS-E01 OVL - Introduction to Assertions
CLICK HERE for a complete list of the seminars in the AVMS European series.]]> info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=9 Read and Download the complete document]]> info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=8 These IP blocks may represent general-purpose processor cores, digital signal processor (DSP) cores, memory controllers, communications functions, etc. Furthermore, this third-party IP, which may account for a large proportion of the overall design, often originates from a number of different IP vendors.
Not surprisingly, due to the fact that each IP block represents a considerable amount of time and investment, the IP vendors wish to guard their secrets. The way this is achieved is to encrypt the source, which means encoding it so as to make it unintelligible to unauthorized parties.
In order to address this issue, the scientists and engineers at Synplicity® have invented (and implemented) an open IP encryption environment that will facilitate the use of protected IP throughout the design flow: from IP vendor to EDA vendor to silicon vendor.
Read and Download the complete document]]> info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100 http://www.edaway.com/news.php?action=details&id_news=2 info@edaway.com NEWS Sun, 11 May 2008 22:00:00 +0100