EDAWAY NEWS

Impulse Selected Edaway for Italy Representation

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100

Impulse serves software and hardware design teams. Aerospace, telecommunications, consumer electronics, research institutions and financial services organizations use Impulse tools. Impulse supports an open C-to-FPGA community with a large membership in Europe, North American and Asia. Impulse strongly endorse tools interoperability and device independence. Impulse is part of an open, vibrant ecosystem of device manufactures, IP library providers, design services and training organizations. Please contact EDAWAY to arrange for a consultation to learn more about the Impulse design environment.

SCI-ME 2.0 support for ASIC Design Emulation.

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100

Aldec Incorporated, a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, announced today the release of HES™ (Hardware Emulation System) 2008.07. The new HES release targets innovative debugging techniques combined with an ESL verification environment. The latest release of HES provides on-chip debugging through a newly integrated logic analyzer core, giving high-visibility to monitor any internal signal for designs verified in the emulator with Accellera standard SCE-MI 2.0.
HES 2008.07 also includes dynamic debugging over Xilinx® readback, for on-the-fly observed signal additions without re-running the design setup process and re-programming HES hardware, support for OVL 2.2 Assertions and additional support for commercial prototyping boards: Synopsys®/Synplicity® HAPS™ 52 and The Dini Group DN9000K10PCI, with Xilinx Virtex-5 devices.

Read the complete document Aldec News Releases

Aldec Joins Altera DO-254 Global Partner Network Providing In-Hardware Verification of ...

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
Aldec provides a cost-effective solution for customers targeting Altera’s Cyclone FPGAs, Stratix FPGAs, Arria GX FPGAs and HardCopy ASICs, which require DO-254 compliance. The verification solution addresses the challenges associated with traditional in-hardware testing using a logic analyzer to validate an FPGA on the final system board. Aldec’s DO-254 CTS solution provides the designer with access to all of the FPGA I/O pins at the board level. The Aldec DO-254 CTS meets customers’ requirements for the DO-254 tool assessment and qualification process and provides the required documentation to meet the DO-254 standard.null Read More

Seminario Aldec “Innovative Design Methodologies for FPGA productivity”

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
Durante l’incontro verranno presentate tutte le novità degli ambienti di progetto, di simulazione e di verifica relativi agli FPGA, che consentono un consistente miglioramento della produttività dei progettisti, caratteristiche che fanno di Aldec uno dei leader mondiali delle metodologie di design. In modo particolare, oltre alle consolidate tecnologie di simulazione e verifica, saranno presentate le soluzioni di debug ed accelerazione hardware, l’integrazione con ambienti di sviluppo, verifica e co-simulazione per applicazioni DSP (Matlab, Simulink, Synplify DSP, System Generator, DSP Builder), e piattaforme di verifica, co-verifica e prototipazione che fanno dei prodotti Aldec una soluzione unica sul mercato.

Aldec Releases Riviera-PRO(TM) 2008.02 with VHDL 2007, SystemC 2.2 and SystemVerilog (DPI)

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
Riviera-PRO offers mixed language verification support for VHDL, Verilog(R), SystemVerilog and SystemC for behavioral, structural and timing simulation of multi-million gate ASIC and FPGA designs. Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC, C/C++, Assertions and EDIF. Riviera-PRO works in command line mode for maximum speed or in state-of-the-art GUI for enhanced editing, tracing, and debugging capabilities, including code coverage and linting. Riviera-PRO is compatible with industry standards and interfaces with popular EDA products such as Synopsys(R) SmartModels(TM), LMTV(TM), Novas(TM), Denali(R), MATLAB(R), and Simulink(R). CLICK HERE to read the complete Press Release

EMPIRE XCcel 5.13

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
This full 3D EM field solver – based on the FDTD (Finite-Difference Time Domain) method – always aims to be the fastest and the most efficient design tool for all kind of design and analysis of RF and microwave devices (antennas, resonators,, etc.), circuits and components. It is designed as an effective engineering tool made ‘by engineers for engineers’, that is both accurate and flexible, able to tackle today’s design complexities as well. Today, EMPIRE XCcel is the most accurate and efficient tool which delivers results in record short time.

EMPIRE XCcel 5.1

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
Features:

Windows Vista Compatibility;
64 bit support for Windows XP and Vista;
Accelerated GUI for very complex structures;
Expert based automatic meshing;
Improved management of imported 3D data;
Speed improvement of open boundary conditions;
Further Kernel speed up (900 MCells / sec);
Lossy Meta Materials Support;

Further details at:

EMPIRE XCcel web site

MicroStripes 7.51

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
This Update contains several important improvements for MicroStripes 7.5, including support for running on Windows Vista. The list of changes included in this Update are described in the readme file.

MicroStripes 7.5

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
http://www.flomerics.com/microstripes

Released version XCcel

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
The new release of the 3D EM field solver Empire™, reveals a completely redesigned and intuitive Graphical User Interface. In addition to new features, like Wizards, Templates and even further speed improvements, it exhibits a vast range of enhancements which will speed up the new user’s learning curve.

Empire XCcel

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
The XCcel features the new GUI, designed from ground-up to deliver truly intuitive and easy to use simulation tool. The discontinued EMPIRE versions were already faster than other simulators in the market.
The XCcel is now twice as fast with Kernel speeds processing up to 450 Mcells/sec, producing very accurate results. Wizards, Templates and its high speed processing makes Xccel the tool of choice for engineering professionals. XCcel features new modules such as Meta Materials, a powerful OPTIMIZER and parallel computing.
If reducing time-to-market, lowering costs and improving design are important to you, then you must consider the XCcel as an indispensable addition to your range of design tools.
This superb and powerful simulator is very much affordable and costs much less compared to other simulators in the market.
XCcel comes with full support provided by engineers at IMST experienced in the study of a wide range of microwave and radio frequency applications.

Aldec European Web Seminar Series

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
This is one of several educational events in the Aldec Verification Methodology Solution (AVMS) series.

Agenda:

- Overview of OVL – Sources and Versions
- OVL Compilation and Management
- Using OVL with HDLs
- Important Global Defines (constants).
- OVL Checkers for Assertions and Functional Coverage

CLICK HERE to register for AVMS-E01 OVL - Introduction to Assertions
CLICK HERE for a complete list of the seminars in the AVMS European series.

Synplicity Open IP Protection Flow in Riviera

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
This new methodology enables easy encryption of IP cores for secure delivery from the IP vendor to the customer. The encryption and decryption involves no action on the side of the customer – all required activities concern IP vendor and tool vendors only. Customers can open delivered IP source but will only see unintelligible, encrypted and encoded text. The compiler of a compatible tool will be able to decrypt the source on-the-fly, leaving no traces that could compromise the security of encryption.
Read and Download the complete document

Synplicity Open IP Encryption Flow

info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
Today's extremely large and complex ASIC and FPGA designs use significant amounts of third-party intellectual property (IP).
These IP blocks may represent general-purpose processor cores, digital signal processor (DSP) cores, memory controllers, communications functions, etc. Furthermore, this third-party IP, which may account for a large proportion of the overall design, often originates from a number of different IP vendors.
Not surprisingly, due to the fact that each IP block represents a considerable amount of time and investment, the IP vendors wish to guard their secrets. The way this is achieved is to encrypt the source, which means encoding it so as to make it unintelligible to unauthorized parties.
In order to address this issue, the scientists and engineers at Synplicity® have invented (and implemented) an open IP encryption environment that will facilitate the use of protected IP throughout the design flow: from IP vendor to EDA vendor to silicon vendor.
Read and Download the complete document

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info@edaway.com — Mon, 06 Sep 2010 22:00:00 +0100
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