Active-HDL

Top Features and Benefits

Project Management

• Unified Team-based Design Management maintains uniformity across local or remote teams

• Configurable FPGA/EDA Flow Manager interfaces with 200+ vendors tools allows teams to remain on one platform throughout FPGA development

Graphical/Text Design Entry

• Quickly deploy designs by using Text, Schematic and State Machine

• Distribute or deliver IPs using more secure and reliable Interoperable Encryption standard

Simulation and Debugging

• Powerful common kernel mixed language simulator that supports VHDL, Verilog, SystemVerilog and SystemC

• Ensure code quality and reliability using graphically interactive debugging and code quality tools

• Perform metrics driven verification to identify unexercised parts of your design using Code Coverage analysis tools

• Improve verification quality  and find more bugs using ABV – Assertion-Based Verification (SVA, PSL)

• Ability to simulate advanced verification constructs like SV Functional Coverage, Constrained Randomization and UVM

• Connect the gap between HDL simulation and high level mathematical modeling environment for DSP blocks using MATLAB®/Simulink® interface

Documentation HTML/PDF

• Abstract design intelligence and represent them in easy to understand graphical form using HDL to schematic converte

• Share designs quickly with auto-generate Design Documentation in HTML and PDF