HeartOS

HeartOS – A POSIX-based Hard Real-time Operating System

HeartOS from DDC-I is a POSIX-based hard real-time operating system that is fast, light and well featured for most for small to medium embedded applications, including safety-critical applications. It is a compliment to DDC-I’s time & space RTOS, Deos™, which is suited for applications that can benefit by multiple assurance levels and space partitioning. HeartOS was designed to operate on 16-bit and 32-bit platforms, however it is configurable without the POSIX layer for memory constrained systems.

Features

Modular & Scalable
POSIX Profile 51 Style Interfaces
Small Footprint
Certifiable to DO-178, Level A
Supports 32 / 16 bit processors and DSP’s
Network Support

The POSIX API

Provides the required POSIX Interfaces
Implemented using the provided core services
Initialization Interfaces
Initializes pre-allocated kernel and internal data structures
Allows configuration of many of the provided services, including number of threads, stack size, priorities, etc.
Run-time interfaces
Provides an interface for the BSP to notify the OS that a system time tick has occurred
Provides hooks for the BSP to notify the OS of exceptions or interrupts which have occurred

Components and Target Support Components

Components

- POSIX Profile 51 Interfaces
- TCP/IP Stack
- Optional DO-178 Certification Artifacts
- OpenArbor Tool Chain

Target Support

- x86 (386, 486, Pentium)
- PowerPC (5xx, 55xx, 603e, 82xx)
- ARM (ARM7, ARM9)
- Others (Call for Availability)

The HeartOS Core

Provides framework to host the POSIX API
Includes thread and list services as well as the interrupt and exception interface and the signal frame
Highly Configurable
Conditional compilation used to completely remove modules which may not be required (e.g. signals)
Reduces the footprint
Deterministic response
All services designed to have a deterministic response time
Scalable
Kernel services designed to be scalable from 16 to 32 bit

BSP and Networking

Provides platform specific initialization of the hardware platform, including: timers, interrupts, and exceptions
Initializes the HeartOS
Forwards OS time tick interrupts to the OS
Forwards unhandled interrupts or exceptions to the OS as necessary

he Hardware Abstraction Layer

Provides an abstract interface to the processing core
Simplifies porting to new processors
Processor specific thread creation and context switching
Interrupt enable/disable services
Considered part of BSP

Networking Features

Low RAM Usage: May be as low as 10K
Low Footprint: 40Kb
Standard BSD: Supports standard BSD socket interface for network
Configurable: Protocol components such as ARP, UDP, TCP, ICM can be conditionally compiled. Each of the components expose useful set of configurable options
Portable: The TCP/IP stack interfaces with the device driver through a Network Abstraction Layer
Zero Copy: The TCP/IP stack uses a network buffer management similar to BSD mbufs to achieve optimum zero copy architecture
Deterministic: All algorithms in the TCP/IP stack are bounded
Standards Compliance: The implementation conforms to RFCs 791, 792, 768, 793 et al
Open Source: HeartOS TCP/IP stack is derived from the Light Weight TCP/IP stack (LWIP), which is quite actively developed by the Open Source Community and deployed in a wide range of product